Logicore IP Is A High-Performance, Low Cost Flexible Solution

The LogiCORE IP Common Public Radio Interface (CPRI) core is a high-performance, low-cost flexible solution for implementation of the CPRI interface. The core can be implemented on UltraScale architecture, Zynq®-7000 All Programmable SoC and 7 series devices. It uses state-of-the-art GTXE2, GTPE2, GTHE2, and GTHE3 transceivers to implement the Physical Layer. A compact and customizable Data Link Layer is implemented in the FPGA logic.

• Designs implemented on UltraScale architecture-based, Zynq-7000, Virtex-7 and Kintex-7 devices operate at line rates of 614.4, 1228.8, 2457.6, 3072, 4915.2, 6144, 9830.4, and 10137.6 Mb/s using GTXE2, GTHE2 or GTHE3 transceivers
• Designs implemented on Artix-7 devices operate at line rates of 614.4, 1228.8, 2457.6, 3072, 4915.2, and 6144 Mb/s using GTPE2 transceivers
• UTRA-FDD I/Q module supporting 1 to 48 Antenna-Carriers per core
• Automatic speed negotiation
• Supports both Fast (Ethernet) and Slow High-Level Data Link Control (HDLC) Control and Management (C&M) channels per CPRI Specification v6.0
• Designed to CPRI Specification v6.0
• Can be configured as master or slave at generation time
• Master core can be switched to operate as a slave through a configuration port
• Suitable for use in both Radio Equipment Controllers (RECs) and Radio Equipment (RE), including multi-hop systems
• Delay measurement capability meets CPRI Requirement 21 per CPRI Specification v6.0
• Core includes the necessary clocking and transceiver logic to enable easy integration into your design
• Synthesizable example design and simple demonstration test bench provided
• Easy-to-use interface for in-phase (I) and quadrature-phase (Q) data and synchronization
• Supports vendor-specific data transport